1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and more particularly, to a semiconductor integrated circuit device provided with a wiring pattern having a long connecting distance.
2. Description of the Prior Art
Recently, semiconductor integrated circuits have been developed with increasingly higher integration densities. Nowadays, semiconductor integrated circuit devices are manufactured having hundreds of thousands of semiconductor elements formed in a single semiconductor chip. However, such a large scale integration gives rise to several problems with respect to the performance of the integrated circuit.
One of the problems is that the signal wiring connecting the semiconductor elements is usually quite long, leading to an increase in the propagation delay time of signal. When it comes to an integrated logic circuit comprising, for example, scores of thousands of logic gates, the average length of the wiring becomes as much as 2 to 3 mm, though the actual length depends on the type, design and manufacturing method of the integrated circuit. The long wiring causes an increase in the stray capacitance attributed to wiring, i.e., ground capacitance of wiring, with the result that the rise time and the fall time of a signal are prolonged, so as to make it difficult to achieve a high speed operation.
FIG. 1, which shows a part of an integrated circuit using GaAs, is intended to explain the problem noted above. As seen from the drawing, the circuit comprises metal-semiconductor type field effect transistors (MES-FET) Q1 to Q3. The transistor Q1 is of a normally on type, i.e., D-FET, and the transistor Q2 is of a normally off type, i.e., E-FET, so as to constitute an inverter, with the transistor Q1 acting as a load and the transistor Q2 as a driver. It is impossible to use MIS-FETs for forming the inverter because it is difficult to form a satisfactory gate insulating film in the case of using a GaAs substrate. The transistor Q3 is a D-FET acting as a current source. The circuit also comprises a Schottky barrier diode D acting as a level shifter. The diode D and transistor Q3 are intended to enable the inverter output voltage applied to a next gate from a node N1 to be controlled within a predetermined level. The particular construction for the level control, which is peculiar to a GaAs logic, is derived from the fact that a MES-FET is used as the transistor Q2 (E-FET) constituting the driver of the inverter. It should be noted that, in the case of a MES-FET, a leak current is likely to flow through its Shottky junction in accordance with an increase in the input voltage. To prevent the problem, it is necessary to control the output taken from the node N1, i.e., the input applied to the logic gate of the subsequent stage, to fall within a predetermined range.
If the wiring extending from the output node N1 to the gate of the subsequent stage is considerably long in the logic gate of the particular construction described above, the ground capacitance of the wiring becomes significantly large as if a large load capacitor C.sub.L of a large capacitance were connected to the node N1, as shown by an imaginary line in the drawing. It follows that it is necessary to perform the charging/discharging of the capacitor C.sub.L in the actual logic action, leading to a low response speed of the device. In order to improve the response speed, it is necessary to sufficiently increase the conductance of the load D-FET Q1, through which flows the charging current, and the current source D-FET Q3, through which flows the discharge current. However, the increase of the conductance noted above gives rise to another problem, i.e., increased power consumption.
A circuit as shown in FIG. 2 is known to the art as a measure for solving the above-noted problem. In the circuit shown in FIG. 2, a bypass capacitor C.sub.F is provided between the node N1 and a node N2 on the anode side of the Shottky diode D shown in FIG. 1. In this case, the charging current is applied to the load capacitor C.sub.L via the Schottky diode D and the bypass capacitor C.sub.F. Also, the discharge current of the load capacitor C.sub.L flows through the D-FET Q3 acting as the current source and through the bypass capacitor C.sub.F into the E-FET Q2 acting as a driver of the inverter. It follows that it is possible to set the direct current of the source current D-FET Q3 to a small value, sufficient for only determining the bias point of the subsequent stage, by setting the impedance of the bypass capacitor C.sub.F with respect to the transient current to a sufficiently small value. As a result, the power consumption can be minimized and the logic action can be carried out at a sufficiently high speed. As a matter of fact, it is reported in "GaAs IC Symposium 1984", page 11, that, if the capacitance of the bypass capacitor C.sub.F is set 3 to 10 times as large as that of the load capacitor C.sub.L derived from the wiring, it is possible to perform a stable operation at a high speed.
The bypass capacitor C.sub.F shown in FIG. 2 includes a first type, which uses a Schottky diode and a second type, which uses a capacitor of a metal-insulator-metal laminated structure. The first type utilizes the capacitance generated when a reverse bias is applied to the Shottky diode. Where the wiring is long, leading to a large load capacitor C.sub.L, however, a very large area is required for forming the bypass capacitor C.sub.F meeting the capacitance of the load capacitor C.sub.L in each of these two types. Naturally, the requirement of the large area makes it difficult to improve the integration density of the integrated circuit. In addition, where a number of wirings of different lengths are included as in a random logic, giving rise to a number of load capacitors C.sub.L of different capacitances, it is necessary to provide a number of bypass capacitors C.sub.F conforming with the load capacitors C.sub.L. In this case, it is very difficult to design the layout of the circuit appropriately.
As described above, a long signal wiring has a detrimental effect on the circuit performance in a large scale integrated circuit. If a bypass capacitor is provided in an attempt to eliminate the defect, a large area is required for providing the bypass capacitor. In addition, the layout design is quite difficult.